LAF 11.0.5 L;

SECTION HEADER;
	DESIGN isp1m 1.0.0;
	DESCRIPTION EP-ROM 27C101 EMURATOR;
END;

SECTION DEVICE;
	TECHNOLOGY pLSI;
	PART pLSI2096-125LQ128;
END;

SECTION LOGICAL;
XPIN A0 BIDI A0 LOCK 37;
XPIN A1 BIDI A1 LOCK 38;
XPIN A2 BIDI A2 LOCK 39;
XPIN A3 BIDI A3 LOCK 40;
XPIN A4 BIDI A4 LOCK 41;
XPIN A5 BIDI A5 LOCK 42;
XPIN A6 BIDI A6 LOCK 43;
XPIN A7 BIDI A7 LOCK 44;
XPIN A8 BIDI A8 LOCK 3;
XPIN A9 BIDI A9 LOCK 4;
XPIN A10 BIDI A10 LOCK 5;
XPIN A11 BIDI A11 LOCK 6;
XPIN A12 BIDI A12 LOCK 7;
XPIN A13 BIDI A13 LOCK 8;
XPIN A14 BIDI A14 LOCK 9;
XPIN A15 BIDI A15 LOCK 10;
XPIN RA16 OUT RA16_PIN;
XPIN EA16 IN EA16 LOCK 16;
XPIN EMCE IN EMCE LOCK 17;
XPIN EMOE IN EMOE LOCK 18;
XPIN AINC IN AINC LOCK 19;
XPIN WR IN WR LOCK 20;
XPIN CLR IN CLR LOCK 21;
XPIN DIR IN DIR LOCK 22;
XPIN BUSENB OUT BUSENB_PIN LOCK 25;
XPIN EMDBEN OUT EMDBEN_PIN LOCK 26;
XPIN ATDBEN OUT ATDBEN_PIN LOCK 27;
XPIN WE OUT WE_PIN LOCK 28;
XPIN CS OUT CS_PIN LOCK 29;
XPIN OE OUT OE_PIN LOCK 30;

NET A0_C SRC A0_C.Z0 DST A0.CLK;

NET A0_AR SRC A0_AR.Z0 DST A0.CD;

NET A0_D SRC A0_D.Z0 DST A0.D0;

NET A0_Q SRC A0.Q0 DST A0_Z.A0 A0_D.A0;

NET A0_OE SRC A0_OE.Z0 DST A0_Z.OE;

NET A0 EXT SRC A0_Z.XB0;

NET A0_PIN SRC A0_Z.Z0 DST A1_D.A1 A2_D.A0 A3_D.A0 A4_D.A0 A5_D.A0
 A6_D.A0 A7_D.A0 A8_D.A0 A9_D.A0 A10_D.A0
 A11_D.A0 A12_D.A0 A13_D.A0 A14_D.A0 A15_D.A0
 A16_D.A0;

NET A1_C SRC A1_C.Z0 DST A1.CLK;

NET A1_AR SRC A1_AR.Z0 DST A1.CD;

NET A1_D SRC A1_D.Z0 DST A1.D0;

NET A1_Q SRC A1.Q0 DST A1_Z.A0 A1_D.A0;

NET A1_OE SRC A1_OE.Z0 DST A1_Z.OE;

NET A1 EXT SRC A1_Z.XB0;

NET A1_PIN SRC A1_Z.Z0 DST A2_D.A2 A3_D.A1 A4_D.A1 A5_D.A1 A6_D.A1
 A7_D.A1 A8_D.A1 A9_D.A1 A10_D.A1 A11_D.A1
 A12_D.A1 A13_D.A1 A14_D.A1 A15_D.A1 A16_D.A1;

NET A2_C SRC A2_C.Z0 DST A2.CLK;

NET A2_AR SRC A2_AR.Z0 DST A2.CD;

NET A2_D SRC A2_D.Z0 DST A2.D0;

NET A2_Q SRC A2.Q0 DST A2_Z.A0 A2_D.A1;

NET A2_OE SRC A2_OE.Z0 DST A2_Z.OE;

NET A2 EXT SRC A2_Z.XB0;

NET A2_PIN SRC A2_Z.Z0 DST A3_D.A3 A4_D.A2 A5_D.A2 A6_D.A2 A7_D.A2
 A8_D.A2 A9_D.A2 A10_D.A2 A11_D.A2 A12_D.A2
 A13_D.A2 A14_D.A2 A15_D.A2 A16_D.A2;

NET A3_C SRC A3_C.Z0 DST A3.CLK;

NET A3_AR SRC A3_AR.Z0 DST A3.CD;

NET A3_D SRC A3_D.Z0 DST A3.D0;

NET A3_Q SRC A3.Q0 DST A3_Z.A0 A3_D.A2;

NET A3_OE SRC A3_OE.Z0 DST A3_Z.OE;

NET A3 EXT SRC A3_Z.XB0;

NET A3_PIN SRC A3_Z.Z0 DST A4_D.A4 A5_D.A3 A6_D.A3 A7_D.A3 A8_D.A3
 A9_D.A3 A10_D.A3 A11_D.A3 A12_D.A3 A13_D.A3
 A14_D.A3 A15_D.A3 A16_D.A3;

NET A4_C SRC A4_C.Z0 DST A4.CLK;

NET A4_AR SRC A4_AR.Z0 DST A4.CD;

NET A4_D SRC A4_D.Z0 DST A4.D0;

NET A4_Q SRC A4.Q0 DST A4_Z.A0 A4_D.A3;

NET A4_OE SRC A4_OE.Z0 DST A4_Z.OE;

NET A4 EXT SRC A4_Z.XB0;

NET A4_PIN SRC A4_Z.Z0 DST A5_D.A5 A6_D.A4 A7_D.A4 A8_D.A4 A9_D.A4
 A10_D.A4 A11_D.A4 A12_D.A4 A13_D.A4 A14_D.A4
 A15_D.A4 A16_D.A4;

NET A5_C SRC A5_C.Z0 DST A5.CLK;

NET A5_AR SRC A5_AR.Z0 DST A5.CD;

NET A5_D SRC A5_D.Z0 DST A5.D0;

NET A5_Q SRC A5.Q0 DST A5_Z.A0 A5_D.A4;

NET A5_OE SRC A5_OE.Z0 DST A5_Z.OE;

NET A5 EXT SRC A5_Z.XB0;

NET A5_PIN SRC A5_Z.Z0 DST A6_D.A6 A7_D.A5 A8_D.A5 A9_D.A5 A10_D.A5
 A11_D.A5 A12_D.A5 A13_D.A5 A14_D.A5 A15_D.A5
 A16_D.A5;

NET A6_C SRC A6_C.Z0 DST A6.CLK;

NET A6_AR SRC A6_AR.Z0 DST A6.CD;

NET A6_D SRC A6_D.Z0 DST A6.D0;

NET A6_Q SRC A6.Q0 DST A6_Z.A0 A6_D.A5;

NET A6_OE SRC A6_OE.Z0 DST A6_Z.OE;

NET A6 EXT SRC A6_Z.XB0;

NET A6_PIN SRC A6_Z.Z0 DST A7_D.A7 A8_D.A6 A9_D.A6 A10_D.A6 A11_D.A6
 A12_D.A6 A13_D.A6 A14_D.A6 A15_D.A6 A16_D.A6;

NET A7_C SRC A7_C.Z0 DST A7.CLK;

NET A7_AR SRC A7_AR.Z0 DST A7.CD;

NET A7_D SRC A7_D.Z0 DST A7.D0;

NET A7_Q SRC A7.Q0 DST A7_Z.A0 A7_D.A6;

NET A7_OE SRC A7_OE.Z0 DST A7_Z.OE;

NET A7 EXT SRC A7_Z.XB0;

NET A7_PIN SRC A7_Z.Z0 DST A8_D.A8 A9_D.A7 A10_D.A7 A11_D.A7 A12_D.A7
 A13_D.A7 A14_D.A7 A15_D.A7 A16_D.A7;

NET A8_C SRC A8_C.Z0 DST A8.CLK;

NET A8_AR SRC A8_AR.Z0 DST A8.CD;

NET A8_D SRC A8_D.Z0 DST A8.D0;

NET A8_Q SRC A8.Q0 DST A8_Z.A0 A8_D.A7;

NET A8_OE SRC A8_OE.Z0 DST A8_Z.OE;

NET A8 EXT SRC A8_Z.XB0;

NET A8_PIN SRC A8_Z.Z0 DST A9_D.A9 A10_D.A8 A11_D.A8 A12_D.A8 A13_D.A8
 A14_D.A8 A15_D.A8 A16_D.A8;

NET A9_C SRC A9_C.Z0 DST A9.CLK;

NET A9_AR SRC A9_AR.Z0 DST A9.CD;

NET A9_D SRC A9_D.Z0 DST A9.D0;

NET A9_Q SRC A9.Q0 DST A9_Z.A0 A9_D.A8;

NET A9_OE SRC A9_OE.Z0 DST A9_Z.OE;

NET A9 EXT SRC A9_Z.XB0;

NET A9_PIN SRC A9_Z.Z0 DST A10_D.A10 A11_D.A9 A12_D.A9 A13_D.A9 A14_D.A9
 A15_D.A9 A16_D.A9;

NET A10_C SRC A10_C.Z0 DST A10.CLK;

NET A10_AR SRC A10_AR.Z0 DST A10.CD;

NET A10_D SRC A10_D.Z0 DST A10.D0;

NET A10_Q SRC A10.Q0 DST A10_Z.A0 A10_D.A9;

NET A10_OE SRC A10_OE.Z0 DST A10_Z.OE;

NET A10 EXT SRC A10_Z.XB0;

NET A10_PIN SRC A10_Z.Z0 DST A11_D.A11 A12_D.A10 A13_D.A10 A14_D.A10 A15_D.A10
 A16_D.A10;

NET A11_C SRC A11_C.Z0 DST A11.CLK;

NET A11_AR SRC A11_AR.Z0 DST A11.CD;

NET A11_D SRC A11_D.Z0 DST A11.D0;

NET A11_Q SRC A11.Q0 DST A11_Z.A0 A11_D.A10;

NET A11_OE SRC A11_OE.Z0 DST A11_Z.OE;

NET A11 EXT SRC A11_Z.XB0;

NET A11_PIN SRC A11_Z.Z0 DST A12_D.A12 A13_D.A11 A14_D.A11 A15_D.A11 A16_D.A11;

NET A12_C SRC A12_C.Z0 DST A12.CLK;

NET A12_AR SRC A12_AR.Z0 DST A12.CD;

NET A12_D SRC A12_D.Z0 DST A12.D0;

NET A12_Q SRC A12.Q0 DST A12_Z.A0 A12_D.A11;

NET A12_OE SRC A12_OE.Z0 DST A12_Z.OE;

NET A12 EXT SRC A12_Z.XB0;

NET A12_PIN SRC A12_Z.Z0 DST A13_D.A13 A14_D.A12 A15_D.A12 A16_D.A12;

NET A13_C SRC A13_C.Z0 DST A13.CLK;

NET A13_AR SRC A13_AR.Z0 DST A13.CD;

NET A13_D SRC A13_D.Z0 DST A13.D0;

NET A13_Q SRC A13.Q0 DST A13_Z.A0 A13_D.A12;

NET A13_OE SRC A13_OE.Z0 DST A13_Z.OE;

NET A13 EXT SRC A13_Z.XB0;

NET A13_PIN SRC A13_Z.Z0 DST A14_D.A14 A15_D.A13 A16_D.A13;

NET A14_C SRC A14_C.Z0 DST A14.CLK;

NET A14_AR SRC A14_AR.Z0 DST A14.CD;

NET A14_D SRC A14_D.Z0 DST A14.D0;

NET A14_Q SRC A14.Q0 DST A14_Z.A0 A14_D.A13;

NET A14_OE SRC A14_OE.Z0 DST A14_Z.OE;

NET A14 EXT SRC A14_Z.XB0;

NET A14_PIN SRC A14_Z.Z0 DST A15_D.A15 A16_D.A14;

NET A15_C SRC A15_C.Z0 DST A15.CLK;

NET A15_AR SRC A15_AR.Z0 DST A15.CD;

NET A15_D SRC A15_D.Z0 DST A15.D0;

NET A15_Q SRC A15.Q0 DST A15_Z.A0 A15_D.A14;

NET A15_OE SRC A15_OE.Z0 DST A15_Z.OE;

NET A15 EXT SRC A15_Z.XB0;

NET A15_PIN SRC A15_Z.Z0 DST A16_D.A16;

NET RA16_PIN EXT SRC RA16.Z0;

NET EA16 EXT DST RA16.A1;

NET EMCE EXT DST EMDBEN_B.A1 CS_B.A1;

NET EMOE EXT DST OE_B.A1;

NET AINC EXT DST A16_C.A0 A15_C.A0 A14_C.A0 A13_C.A0 A12_C.A0
 A11_C.A0 A10_C.A0 A9_C.A0 A8_C.A0 A7_C.A0
 A6_C.A0 A5_C.A0 A4_C.A0 A3_C.A0 A2_C.A0
 A1_C.A0 A0_C.A0;

NET WR EXT DST WE_B.A1;

NET CLR EXT DST A16_AR.A0 A15_AR.A0 A14_AR.A0 A13_AR.A0 A12_AR.A0
 A11_AR.A0 A10_AR.A0 A9_AR.A0 A8_AR.A0 A7_AR.A0
 A6_AR.A0 A5_AR.A0 A4_AR.A0 A3_AR.A0 A2_AR.A0
 A1_AR.A0 A0_AR.A0;

NET DIR EXT DST RA16.A0 BUSENB_B.A0 EMDBEN_B.A0 ATDBEN_B.A0 WE_B.A0
 CS_B.A0 OE_B.A0 A15_OE.A0 A14_OE.A0 A13_OE.A0
 A12_OE.A0 A11_OE.A0 A10_OE.A0 A9_OE.A0 A8_OE.A0
 A7_OE.A0 A6_OE.A0 A5_OE.A0 A4_OE.A0 A3_OE.A0
 A2_OE.A0 A1_OE.A0 A0_OE.A0;

NET BUSENB_PIN EXT SRC BUSENB.ZN0;

NET EMDBEN_PIN EXT SRC EMDBEN.ZN0;

NET ATDBEN_PIN EXT SRC ATDBEN.ZN0;

NET WE_PIN EXT SRC WE.ZN0;

NET CS_PIN EXT SRC CS.ZN0;

NET OE_PIN EXT SRC OE.ZN0;

NET A16_C SRC A16_C.Z0 DST A16.CLK;

NET A16_AR SRC A16_AR.Z0 DST A16.CD;

NET A16_D SRC A16_D.Z0 DST A16.D0;

NET A16 SRC A16.Q0 DST A16_Q.A0 RA16.A2;

NET A16_Q SRC A16_Q.Z0 DST A16_D.A15;

NET BUSENB_B SRC BUSENB_B.Z0 DST BUSENB.A0;

NET EMDBEN_B SRC EMDBEN_B.Z0 DST EMDBEN.A0;

NET ATDBEN_B SRC ATDBEN_B.Z0 DST ATDBEN.A0;

NET WE_B SRC WE_B.Z0 DST WE.A0;

NET CS_B SRC CS_B.Z0 DST CS.A0;

NET OE_B SRC OE_B.Z0 DST OE.A0;

SYM PLA RA16;
	PIN A0 IN DIR;
	PIN A1 IN EA16;
	PIN A2 IN A16;
	PIN Z0 OUT RA16_PIN;
	BEGIN_PLA
	01- 1
	1-1 1
	END_PLA
END;

SYM PLA BUSENB_B;
	PIN A0 IN DIR;
	PIN Z0 OUT BUSENB_B;
	BEGIN_PLA
	0 1
	END_PLA
END;

SYM INV BUSENB;
	PIN A0 IN BUSENB_B;
	PIN ZN0 OUT BUSENB_PIN;
END;

SYM PLA EMDBEN_B;
	PIN A0 IN DIR;
	PIN A1 IN EMCE;
	PIN Z0 OUT EMDBEN_B;
	BEGIN_PLA
	00 1
	END_PLA
END;

SYM INV EMDBEN;
	PIN A0 IN EMDBEN_B;
	PIN ZN0 OUT EMDBEN_PIN;
END;

SYM PLA ATDBEN_B;
	PIN A0 IN DIR;
	PIN Z0 OUT ATDBEN_B;
	BEGIN_PLA
	1 1
	END_PLA
END;

SYM INV ATDBEN;
	PIN A0 IN ATDBEN_B;
	PIN ZN0 OUT ATDBEN_PIN;
END;

SYM PLA WE_B;
	PIN A0 IN DIR;
	PIN A1 IN WR;
	PIN Z0 OUT WE_B;
	BEGIN_PLA
	11 1
	END_PLA
END;

SYM INV WE;
	PIN A0 IN WE_B;
	PIN ZN0 OUT WE_PIN;
END;

SYM PLA CS_B;
	PIN A0 IN DIR;
	PIN A1 IN EMCE;
	PIN Z0 OUT CS_B;
	BEGIN_PLA
	1- 1
	-0 1
	END_PLA
END;

SYM INV CS;
	PIN A0 IN CS_B;
	PIN ZN0 OUT CS_PIN;
END;

SYM PLA OE_B;
	PIN A0 IN DIR;
	PIN A1 IN EMOE;
	PIN Z0 OUT OE_B;
	BEGIN_PLA
	00 1
	END_PLA
END;

SYM INV OE;
	PIN A0 IN OE_B;
	PIN ZN0 OUT OE_PIN;
END;

SYM PLA A16_C;
	PIN A0 IN AINC;
	PIN Z0 OUT A16_C;
	BEGIN_PLA
	1 1
	END_PLA
END;

SYM PLA A15_C;
	PIN A0 IN AINC;
	PIN Z0 OUT A15_C;
	BEGIN_PLA
	1 1
	END_PLA
END;

SYM PLA A14_C;
	PIN A0 IN AINC;
	PIN Z0 OUT A14_C;
	BEGIN_PLA
	1 1
	END_PLA
END;

SYM PLA A13_C;
	PIN A0 IN AINC;
	PIN Z0 OUT A13_C;
	BEGIN_PLA
	1 1
	END_PLA
END;

SYM PLA A12_C;
	PIN A0 IN AINC;
	PIN Z0 OUT A12_C;
	BEGIN_PLA
	1 1
	END_PLA
END;

SYM PLA A11_C;
	PIN A0 IN AINC;
	PIN Z0 OUT A11_C;
	BEGIN_PLA
	1 1
	END_PLA
END;

SYM PLA A10_C;
	PIN A0 IN AINC;
	PIN Z0 OUT A10_C;
	BEGIN_PLA
	1 1
	END_PLA
END;

SYM PLA A9_C;
	PIN A0 IN AINC;
	PIN Z0 OUT A9_C;
	BEGIN_PLA
	1 1
	END_PLA
END;

SYM PLA A8_C;
	PIN A0 IN AINC;
	PIN Z0 OUT A8_C;
	BEGIN_PLA
	1 1
	END_PLA
END;

SYM PLA A7_C;
	PIN A0 IN AINC;
	PIN Z0 OUT A7_C;
	BEGIN_PLA
	1 1
	END_PLA
END;

SYM PLA A6_C;
	PIN A0 IN AINC;
	PIN Z0 OUT A6_C;
	BEGIN_PLA
	1 1
	END_PLA
END;

SYM PLA A5_C;
	PIN A0 IN AINC;
	PIN Z0 OUT A5_C;
	BEGIN_PLA
	1 1
	END_PLA
END;

SYM PLA A4_C;
	PIN A0 IN AINC;
	PIN Z0 OUT A4_C;
	BEGIN_PLA
	1 1
	END_PLA
END;

SYM PLA A3_C;
	PIN A0 IN AINC;
	PIN Z0 OUT A3_C;
	BEGIN_PLA
	1 1
	END_PLA
END;

SYM PLA A2_C;
	PIN A0 IN AINC;
	PIN Z0 OUT A2_C;
	BEGIN_PLA
	1 1
	END_PLA
END;

SYM PLA A1_C;
	PIN A0 IN AINC;
	PIN Z0 OUT A1_C;
	BEGIN_PLA
	1 1
	END_PLA
END;

SYM PLA A0_C;
	PIN A0 IN AINC;
	PIN Z0 OUT A0_C;
	BEGIN_PLA
	1 1
	END_PLA
END;

SYM PLA A16_AR;
	PIN A0 IN CLR;
	PIN Z0 OUT A16_AR;
	BEGIN_PLA
	0 1
	END_PLA
END;

SYM PLA A15_AR;
	PIN A0 IN CLR;
	PIN Z0 OUT A15_AR;
	BEGIN_PLA
	0 1
	END_PLA
END;

SYM PLA A14_AR;
	PIN A0 IN CLR;
	PIN Z0 OUT A14_AR;
	BEGIN_PLA
	0 1
	END_PLA
END;

SYM PLA A13_AR;
	PIN A0 IN CLR;
	PIN Z0 OUT A13_AR;
	BEGIN_PLA
	0 1
	END_PLA
END;

SYM PLA A12_AR;
	PIN A0 IN CLR;
	PIN Z0 OUT A12_AR;
	BEGIN_PLA
	0 1
	END_PLA
END;

SYM PLA A11_AR;
	PIN A0 IN CLR;
	PIN Z0 OUT A11_AR;
	BEGIN_PLA
	0 1
	END_PLA
END;

SYM PLA A10_AR;
	PIN A0 IN CLR;
	PIN Z0 OUT A10_AR;
	BEGIN_PLA
	0 1
	END_PLA
END;

SYM PLA A9_AR;
	PIN A0 IN CLR;
	PIN Z0 OUT A9_AR;
	BEGIN_PLA
	0 1
	END_PLA
END;

SYM PLA A8_AR;
	PIN A0 IN CLR;
	PIN Z0 OUT A8_AR;
	BEGIN_PLA
	0 1
	END_PLA
END;

SYM PLA A7_AR;
	PIN A0 IN CLR;
	PIN Z0 OUT A7_AR;
	BEGIN_PLA
	0 1
	END_PLA
END;

SYM PLA A6_AR;
	PIN A0 IN CLR;
	PIN Z0 OUT A6_AR;
	BEGIN_PLA
	0 1
	END_PLA
END;

SYM PLA A5_AR;
	PIN A0 IN CLR;
	PIN Z0 OUT A5_AR;
	BEGIN_PLA
	0 1
	END_PLA
END;

SYM PLA A4_AR;
	PIN A0 IN CLR;
	PIN Z0 OUT A4_AR;
	BEGIN_PLA
	0 1
	END_PLA
END;

SYM PLA A3_AR;
	PIN A0 IN CLR;
	PIN Z0 OUT A3_AR;
	BEGIN_PLA
	0 1
	END_PLA
END;

SYM PLA A2_AR;
	PIN A0 IN CLR;
	PIN Z0 OUT A2_AR;
	BEGIN_PLA
	0 1
	END_PLA
END;

SYM PLA A1_AR;
	PIN A0 IN CLR;
	PIN Z0 OUT A1_AR;
	BEGIN_PLA
	0 1
	END_PLA
END;

SYM PLA A0_AR;
	PIN A0 IN CLR;
	PIN Z0 OUT A0_AR;
	BEGIN_PLA
	0 1
	END_PLA
END;

SYM PLA A15_OE;
	PIN A0 IN DIR;
	PIN Z0 OUT A15_OE;
	BEGIN_PLA
	1 1
	END_PLA
END;

SYM PLA A14_OE;
	PIN A0 IN DIR;
	PIN Z0 OUT A14_OE;
	BEGIN_PLA
	1 1
	END_PLA
END;

SYM PLA A13_OE;
	PIN A0 IN DIR;
	PIN Z0 OUT A13_OE;
	BEGIN_PLA
	1 1
	END_PLA
END;

SYM PLA A12_OE;
	PIN A0 IN DIR;
	PIN Z0 OUT A12_OE;
	BEGIN_PLA
	1 1
	END_PLA
END;

SYM PLA A11_OE;
	PIN A0 IN DIR;
	PIN Z0 OUT A11_OE;
	BEGIN_PLA
	1 1
	END_PLA
END;

SYM PLA A10_OE;
	PIN A0 IN DIR;
	PIN Z0 OUT A10_OE;
	BEGIN_PLA
	1 1
	END_PLA
END;

SYM PLA A9_OE;
	PIN A0 IN DIR;
	PIN Z0 OUT A9_OE;
	BEGIN_PLA
	1 1
	END_PLA
END;

SYM PLA A8_OE;
	PIN A0 IN DIR;
	PIN Z0 OUT A8_OE;
	BEGIN_PLA
	1 1
	END_PLA
END;

SYM PLA A7_OE;
	PIN A0 IN DIR;
	PIN Z0 OUT A7_OE;
	BEGIN_PLA
	1 1
	END_PLA
END;

SYM PLA A6_OE;
	PIN A0 IN DIR;
	PIN Z0 OUT A6_OE;
	BEGIN_PLA
	1 1
	END_PLA
END;

SYM PLA A5_OE;
	PIN A0 IN DIR;
	PIN Z0 OUT A5_OE;
	BEGIN_PLA
	1 1
	END_PLA
END;

SYM PLA A4_OE;
	PIN A0 IN DIR;
	PIN Z0 OUT A4_OE;
	BEGIN_PLA
	1 1
	END_PLA
END;

SYM PLA A3_OE;
	PIN A0 IN DIR;
	PIN Z0 OUT A3_OE;
	BEGIN_PLA
	1 1
	END_PLA
END;

SYM PLA A2_OE;
	PIN A0 IN DIR;
	PIN Z0 OUT A2_OE;
	BEGIN_PLA
	1 1
	END_PLA
END;

SYM PLA A1_OE;
	PIN A0 IN DIR;
	PIN Z0 OUT A1_OE;
	BEGIN_PLA
	1 1
	END_PLA
END;

SYM PLA A0_OE;
	PIN A0 IN DIR;
	PIN Z0 OUT A0_OE;
	BEGIN_PLA
	1 1
	END_PLA
END;

SYM PLA A0_D;
	PIN A0 IN A0_Q;
	PIN Z0 OUT A0_D;
	BEGIN_PLA
	0 1
	END_PLA
END;

SYM PLA A1_D;
	PIN A0 IN A1_Q;
	PIN A1 IN A0_PIN;
	PIN Z0 OUT A1_D;
	BEGIN_PLA
	01 1
	10 1
	END_PLA
END;

SYM PLA A2_D;
	PIN A0 IN A0_PIN;
	PIN A1 IN A2_Q;
	PIN A2 IN A1_PIN;
	PIN Z0 OUT A2_D;
	BEGIN_PLA
	01- 1
	101 1
	-10 1
	END_PLA
END;

SYM PLA A3_D;
	PIN A0 IN A0_PIN;
	PIN A1 IN A1_PIN;
	PIN A2 IN A3_Q;
	PIN A3 IN A2_PIN;
	PIN Z0 OUT A3_D;
	BEGIN_PLA
	0-1- 1
	-01- 1
	1101 1
	--10 1
	END_PLA
END;

SYM PLA A4_D;
	PIN A0 IN A0_PIN;
	PIN A1 IN A1_PIN;
	PIN A2 IN A2_PIN;
	PIN A3 IN A4_Q;
	PIN A4 IN A3_PIN;
	PIN Z0 OUT A4_D;
	BEGIN_PLA
	0--1- 1
	-0-1- 1
	--01- 1
	11101 1
	---10 1
	END_PLA
END;

SYM PLA A5_D;
	PIN A0 IN A0_PIN;
	PIN A1 IN A1_PIN;
	PIN A2 IN A2_PIN;
	PIN A3 IN A3_PIN;
	PIN A4 IN A5_Q;
	PIN A5 IN A4_PIN;
	PIN Z0 OUT A5_D;
	BEGIN_PLA
	0---1- 1
	-0--1- 1
	--0-1- 1
	---01- 1
	111101 1
	----10 1
	END_PLA
END;

SYM PLA A6_D;
	PIN A0 IN A0_PIN;
	PIN A1 IN A1_PIN;
	PIN A2 IN A2_PIN;
	PIN A3 IN A3_PIN;
	PIN A4 IN A4_PIN;
	PIN A5 IN A6_Q;
	PIN A6 IN A5_PIN;
	PIN Z0 OUT A6_D;
	BEGIN_PLA
	0----1- 1
	-0---1- 1
	--0--1- 1
	---0-1- 1
	----01- 1
	1111101 1
	-----10 1
	END_PLA
END;

SYM PLA A7_D;
	PIN A0 IN A0_PIN;
	PIN A1 IN A1_PIN;
	PIN A2 IN A2_PIN;
	PIN A3 IN A3_PIN;
	PIN A4 IN A4_PIN;
	PIN A5 IN A5_PIN;
	PIN A6 IN A7_Q;
	PIN A7 IN A6_PIN;
	PIN Z0 OUT A7_D;
	BEGIN_PLA
	0-----1- 1
	-0----1- 1
	--0---1- 1
	---0--1- 1
	----0-1- 1
	-----01- 1
	11111101 1
	------10 1
	END_PLA
END;

SYM PLA A8_D;
	PIN A0 IN A0_PIN;
	PIN A1 IN A1_PIN;
	PIN A2 IN A2_PIN;
	PIN A3 IN A3_PIN;
	PIN A4 IN A4_PIN;
	PIN A5 IN A5_PIN;
	PIN A6 IN A6_PIN;
	PIN A7 IN A8_Q;
	PIN A8 IN A7_PIN;
	PIN Z0 OUT A8_D;
	BEGIN_PLA
	0------1- 1
	-0-----1- 1
	--0----1- 1
	---0---1- 1
	----0--1- 1
	-----0-1- 1
	------01- 1
	111111101 1
	-------10 1
	END_PLA
END;

SYM PLA A9_D;
	PIN A0 IN A0_PIN;
	PIN A1 IN A1_PIN;
	PIN A2 IN A2_PIN;
	PIN A3 IN A3_PIN;
	PIN A4 IN A4_PIN;
	PIN A5 IN A5_PIN;
	PIN A6 IN A6_PIN;
	PIN A7 IN A7_PIN;
	PIN A8 IN A9_Q;
	PIN A9 IN A8_PIN;
	PIN Z0 OUT A9_D;
	BEGIN_PLA
	0-------1- 1
	-0------1- 1
	--0-----1- 1
	---0----1- 1
	----0---1- 1
	-----0--1- 1
	------0-1- 1
	-------01- 1
	1111111101 1
	--------10 1
	END_PLA
END;

SYM PLA A10_D;
	PIN A0 IN A0_PIN;
	PIN A1 IN A1_PIN;
	PIN A2 IN A2_PIN;
	PIN A3 IN A3_PIN;
	PIN A4 IN A4_PIN;
	PIN A5 IN A5_PIN;
	PIN A6 IN A6_PIN;
	PIN A7 IN A7_PIN;
	PIN A8 IN A8_PIN;
	PIN A9 IN A10_Q;
	PIN A10 IN A9_PIN;
	PIN Z0 OUT A10_D;
	BEGIN_PLA
	0--------1- 1
	-0-------1- 1
	--0------1- 1
	---0-----1- 1
	----0----1- 1
	-----0---1- 1
	------0--1- 1
	-------0-1- 1
	--------01- 1
	11111111101 1
	---------10 1
	END_PLA
END;

SYM PLA A11_D;
	PIN A0 IN A0_PIN;
	PIN A1 IN A1_PIN;
	PIN A2 IN A2_PIN;
	PIN A3 IN A3_PIN;
	PIN A4 IN A4_PIN;
	PIN A5 IN A5_PIN;
	PIN A6 IN A6_PIN;
	PIN A7 IN A7_PIN;
	PIN A8 IN A8_PIN;
	PIN A9 IN A9_PIN;
	PIN A10 IN A11_Q;
	PIN A11 IN A10_PIN;
	PIN Z0 OUT A11_D;
	BEGIN_PLA
	0---------1- 1
	-0--------1- 1
	--0-------1- 1
	---0------1- 1
	----0-----1- 1
	-----0----1- 1
	------0---1- 1
	-------0--1- 1
	--------0-1- 1
	---------01- 1
	111111111101 1
	----------10 1
	END_PLA
END;

SYM PLA A12_D;
	PIN A0 IN A0_PIN;
	PIN A1 IN A1_PIN;
	PIN A2 IN A2_PIN;
	PIN A3 IN A3_PIN;
	PIN A4 IN A4_PIN;
	PIN A5 IN A5_PIN;
	PIN A6 IN A6_PIN;
	PIN A7 IN A7_PIN;
	PIN A8 IN A8_PIN;
	PIN A9 IN A9_PIN;
	PIN A10 IN A10_PIN;
	PIN A11 IN A12_Q;
	PIN A12 IN A11_PIN;
	PIN Z0 OUT A12_D;
	BEGIN_PLA
	0----------1- 1
	-0---------1- 1
	--0--------1- 1
	---0-------1- 1
	----0------1- 1
	-----0-----1- 1
	------0----1- 1
	-------0---1- 1
	--------0--1- 1
	---------0-1- 1
	----------01- 1
	1111111111101 1
	-----------10 1
	END_PLA
END;

SYM PLA A13_D;
	PIN A0 IN A0_PIN;
	PIN A1 IN A1_PIN;
	PIN A2 IN A2_PIN;
	PIN A3 IN A3_PIN;
	PIN A4 IN A4_PIN;
	PIN A5 IN A5_PIN;
	PIN A6 IN A6_PIN;
	PIN A7 IN A7_PIN;
	PIN A8 IN A8_PIN;
	PIN A9 IN A9_PIN;
	PIN A10 IN A10_PIN;
	PIN A11 IN A11_PIN;
	PIN A12 IN A13_Q;
	PIN A13 IN A12_PIN;
	PIN Z0 OUT A13_D;
	BEGIN_PLA
	0-----------1- 1
	-0----------1- 1
	--0---------1- 1
	---0--------1- 1
	----0-------1- 1
	-----0------1- 1
	------0-----1- 1
	-------0----1- 1
	--------0---1- 1
	---------0--1- 1
	----------0-1- 1
	-----------01- 1
	11111111111101 1
	------------10 1
	END_PLA
END;

SYM PLA A14_D;
	PIN A0 IN A0_PIN;
	PIN A1 IN A1_PIN;
	PIN A2 IN A2_PIN;
	PIN A3 IN A3_PIN;
	PIN A4 IN A4_PIN;
	PIN A5 IN A5_PIN;
	PIN A6 IN A6_PIN;
	PIN A7 IN A7_PIN;
	PIN A8 IN A8_PIN;
	PIN A9 IN A9_PIN;
	PIN A10 IN A10_PIN;
	PIN A11 IN A11_PIN;
	PIN A12 IN A12_PIN;
	PIN A13 IN A14_Q;
	PIN A14 IN A13_PIN;
	PIN Z0 OUT A14_D;
	BEGIN_PLA
	0------------1- 1
	-0-----------1- 1
	--0----------1- 1
	---0---------1- 1
	----0--------1- 1
	-----0-------1- 1
	------0------1- 1
	-------0-----1- 1
	--------0----1- 1
	---------0---1- 1
	----------0--1- 1
	-----------0-1- 1
	------------01- 1
	111111111111101 1
	-------------10 1
	END_PLA
END;

SYM PLA A15_D;
	PIN A0 IN A0_PIN;
	PIN A1 IN A1_PIN;
	PIN A2 IN A2_PIN;
	PIN A3 IN A3_PIN;
	PIN A4 IN A4_PIN;
	PIN A5 IN A5_PIN;
	PIN A6 IN A6_PIN;
	PIN A7 IN A7_PIN;
	PIN A8 IN A8_PIN;
	PIN A9 IN A9_PIN;
	PIN A10 IN A10_PIN;
	PIN A11 IN A11_PIN;
	PIN A12 IN A12_PIN;
	PIN A13 IN A13_PIN;
	PIN A14 IN A15_Q;
	PIN A15 IN A14_PIN;
	PIN Z0 OUT A15_D;
	BEGIN_PLA
	0-------------1- 1
	-0------------1- 1
	--0-----------1- 1
	---0----------1- 1
	----0---------1- 1
	-----0--------1- 1
	------0-------1- 1
	-------0------1- 1
	--------0-----1- 1
	---------0----1- 1
	----------0---1- 1
	-----------0--1- 1
	------------0-1- 1
	-------------01- 1
	1111111111111101 1
	--------------10 1
	END_PLA
END;

SYM PLA A16_D;
	PIN A0 IN A0_PIN;
	PIN A1 IN A1_PIN;
	PIN A2 IN A2_PIN;
	PIN A3 IN A3_PIN;
	PIN A4 IN A4_PIN;
	PIN A5 IN A5_PIN;
	PIN A6 IN A6_PIN;
	PIN A7 IN A7_PIN;
	PIN A8 IN A8_PIN;
	PIN A9 IN A9_PIN;
	PIN A10 IN A10_PIN;
	PIN A11 IN A11_PIN;
	PIN A12 IN A12_PIN;
	PIN A13 IN A13_PIN;
	PIN A14 IN A14_PIN;
	PIN A15 IN A16_Q;
	PIN A16 IN A15_PIN;
	PIN Z0 OUT A16_D;
	BEGIN_PLA
	0--------------1- 1
	-0-------------1- 1
	--0------------1- 1
	---0-----------1- 1
	----0----------1- 1
	-----0---------1- 1
	------0--------1- 1
	-------0-------1- 1
	--------0------1- 1
	---------0-----1- 1
	----------0----1- 1
	-----------0---1- 1
	------------0--1- 1
	-------------0-1- 1
	--------------01- 1
	11111111111111101 1
	---------------10 1
	END_PLA
END;

SYM FD21 A0;
	PIN D0 IN A0_D;
	PIN CD IN A0_AR;
	PIN CLK IN A0_C;
	PIN Q0 OUT A0_Q;
END;

SYM XBIDI1 A0_Z;
	PIN A0 IN A0_Q;
	PIN OE IN A0_OE;
	PIN XB0 BIDI A0;
	PIN Z0 OUT A0_PIN;
END;

SYM FD21 A1;
	PIN D0 IN A1_D;
	PIN CD IN A1_AR;
	PIN CLK IN A1_C;
	PIN Q0 OUT A1_Q;
END;

SYM XBIDI1 A1_Z;
	PIN A0 IN A1_Q;
	PIN OE IN A1_OE;
	PIN XB0 BIDI A1;
	PIN Z0 OUT A1_PIN;
END;

SYM FD21 A2;
	PIN D0 IN A2_D;
	PIN CD IN A2_AR;
	PIN CLK IN A2_C;
	PIN Q0 OUT A2_Q;
END;

SYM XBIDI1 A2_Z;
	PIN A0 IN A2_Q;
	PIN OE IN A2_OE;
	PIN XB0 BIDI A2;
	PIN Z0 OUT A2_PIN;
END;

SYM FD21 A3;
	PIN D0 IN A3_D;
	PIN CD IN A3_AR;
	PIN CLK IN A3_C;
	PIN Q0 OUT A3_Q;
END;

SYM XBIDI1 A3_Z;
	PIN A0 IN A3_Q;
	PIN OE IN A3_OE;
	PIN XB0 BIDI A3;
	PIN Z0 OUT A3_PIN;
END;

SYM FD21 A4;
	PIN D0 IN A4_D;
	PIN CD IN A4_AR;
	PIN CLK IN A4_C;
	PIN Q0 OUT A4_Q;
END;

SYM XBIDI1 A4_Z;
	PIN A0 IN A4_Q;
	PIN OE IN A4_OE;
	PIN XB0 BIDI A4;
	PIN Z0 OUT A4_PIN;
END;

SYM FD21 A5;
	PIN D0 IN A5_D;
	PIN CD IN A5_AR;
	PIN CLK IN A5_C;
	PIN Q0 OUT A5_Q;
END;

SYM XBIDI1 A5_Z;
	PIN A0 IN A5_Q;
	PIN OE IN A5_OE;
	PIN XB0 BIDI A5;
	PIN Z0 OUT A5_PIN;
END;

SYM FD21 A6;
	PIN D0 IN A6_D;
	PIN CD IN A6_AR;
	PIN CLK IN A6_C;
	PIN Q0 OUT A6_Q;
END;

SYM XBIDI1 A6_Z;
	PIN A0 IN A6_Q;
	PIN OE IN A6_OE;
	PIN XB0 BIDI A6;
	PIN Z0 OUT A6_PIN;
END;

SYM FD21 A7;
	PIN D0 IN A7_D;
	PIN CD IN A7_AR;
	PIN CLK IN A7_C;
	PIN Q0 OUT A7_Q;
END;

SYM XBIDI1 A7_Z;
	PIN A0 IN A7_Q;
	PIN OE IN A7_OE;
	PIN XB0 BIDI A7;
	PIN Z0 OUT A7_PIN;
END;

SYM FD21 A8;
	PIN D0 IN A8_D;
	PIN CD IN A8_AR;
	PIN CLK IN A8_C;
	PIN Q0 OUT A8_Q;
END;

SYM XBIDI1 A8_Z;
	PIN A0 IN A8_Q;
	PIN OE IN A8_OE;
	PIN XB0 BIDI A8;
	PIN Z0 OUT A8_PIN;
END;

SYM FD21 A9;
	PIN D0 IN A9_D;
	PIN CD IN A9_AR;
	PIN CLK IN A9_C;
	PIN Q0 OUT A9_Q;
END;

SYM XBIDI1 A9_Z;
	PIN A0 IN A9_Q;
	PIN OE IN A9_OE;
	PIN XB0 BIDI A9;
	PIN Z0 OUT A9_PIN;
END;

SYM FD21 A10;
	PIN D0 IN A10_D;
	PIN CD IN A10_AR;
	PIN CLK IN A10_C;
	PIN Q0 OUT A10_Q;
END;

SYM XBIDI1 A10_Z;
	PIN A0 IN A10_Q;
	PIN OE IN A10_OE;
	PIN XB0 BIDI A10;
	PIN Z0 OUT A10_PIN;
END;

SYM FD21 A11;
	PIN D0 IN A11_D;
	PIN CD IN A11_AR;
	PIN CLK IN A11_C;
	PIN Q0 OUT A11_Q;
END;

SYM XBIDI1 A11_Z;
	PIN A0 IN A11_Q;
	PIN OE IN A11_OE;
	PIN XB0 BIDI A11;
	PIN Z0 OUT A11_PIN;
END;

SYM FD21 A12;
	PIN D0 IN A12_D;
	PIN CD IN A12_AR;
	PIN CLK IN A12_C;
	PIN Q0 OUT A12_Q;
END;

SYM XBIDI1 A12_Z;
	PIN A0 IN A12_Q;
	PIN OE IN A12_OE;
	PIN XB0 BIDI A12;
	PIN Z0 OUT A12_PIN;
END;

SYM FD21 A13;
	PIN D0 IN A13_D;
	PIN CD IN A13_AR;
	PIN CLK IN A13_C;
	PIN Q0 OUT A13_Q;
END;

SYM XBIDI1 A13_Z;
	PIN A0 IN A13_Q;
	PIN OE IN A13_OE;
	PIN XB0 BIDI A13;
	PIN Z0 OUT A13_PIN;
END;

SYM FD21 A14;
	PIN D0 IN A14_D;
	PIN CD IN A14_AR;
	PIN CLK IN A14_C;
	PIN Q0 OUT A14_Q;
END;

SYM XBIDI1 A14_Z;
	PIN A0 IN A14_Q;
	PIN OE IN A14_OE;
	PIN XB0 BIDI A14;
	PIN Z0 OUT A14_PIN;
END;

SYM FD21 A15;
	PIN D0 IN A15_D;
	PIN CD IN A15_AR;
	PIN CLK IN A15_C;
	PIN Q0 OUT A15_Q;
END;

SYM XBIDI1 A15_Z;
	PIN A0 IN A15_Q;
	PIN OE IN A15_OE;
	PIN XB0 BIDI A15;
	PIN Z0 OUT A15_PIN;
END;

SYM FD21 A16;
	PIN D0 IN A16_D;
	PIN CD IN A16_AR;
	PIN CLK IN A16_C;
	PIN Q0 OUT A16;
END;

SYM BUF A16_Q;
	PIN A0 IN A16;
	PIN Z0 OUT A16_Q;
END;

END;

END;