

	 Table 5. Arithmetic and Logical Instructions

Mne-			  Operation						Addressing Mode							Status
monic	M/X	E=1 or			E = 0 and	               dir, dir, (dir) (dir, (dir) [dir] abs abs, abs, absl absl d,s (d,s)
		E=0 and M/X=1		M/X = 0		Immed Accu dir   x    y          x)   ,y               x    y        ,x        ,y	N V M X D I Z C

ADC	Pm	AL + B + Pc -> AL	A + W + Pc -> A	 69        65   75         72    61   71    67    6D  7D   79   6F   7F   63   73	N V . . . . Z C
AND	Pm	AL /\B -> AL		A /\W -> A	 29        25   35         32    21   31    27    2D  3D   39   2F   3F   23   33	N . . . . . Z .
ASL	Pm	Pc <-B <- 0		Pc <- W <- 0	      0A   06   16				  0E  1E				N . . . . . Z C
BIT	Pm	AL /\B			A /\W		 89        24   34				  2C  3C				N V . . . . Z .

CMP	Pm	AL - B			A - W		 C9        C5   D5         D2    C1   D1    C7    CD  DD   D9   CF   DF   C3   D3	N . . . . . Z C
CPX	Px	XL - B			X - W		 E0        E4					  EC					N . . . . . Z C
CPY	Px	YL - B			Y - W		 C0        C4					  CC					N . . . . . Z C
DEC	Pm	B  - 1 -> B		W - 1 -> W	      3A   C6   D6				  CE  DE				N . . . . . Z .

EOR	Pm	AL V- B -> AL		A V- W -> A	 49        45   55         52    41   51    47    4D  5D   59   4F   5F   43   53	N . . . . . Z .
INC	Pm	B  + 1 -> B		W + 1 -> W	      1A   E6   F6				  EE  FE				N . . . . . Z .
LDA	Pm	B  -> AL		W -> A		 A9        A5   B5         B2    A1   B1    B7    AD  BD   B9   AF   BF   A3   B3	N . . . . . Z .
LDX	Px	B  -> XL		W -> X		 A2        A6         B6			  AE       BE				N . . . . . Z .

LDY	Px	B  -> YL		W -> Y		 A0        A4   B4				  AC  BC				N . . . . . Z .
LSR	Pm	0  -> B -> Pc		0 -> W -> Pc	      4A   46   56				  4E  5E				0 . . . . . Z C
ORA	Pm	AL V B -> AL		A V W -> A	 09        05   15         12    01   11    17    0D  1D   19   0F   1F   03   13	N . . . . . Z .
ROL	Pm	Pc <- B <- Pc		Pc <- W <- Pc	      2A   26   36				  2E  3E				N . . . . . Z C

ROR	Pm	Pc -> B -> Pc		Pc -> W -> Pc	      6A   66   76				  6E  7E				N . . . . . Z C
SBC	Pm	AL - B - Pc -> AL	A - W - Pc -> A	 E9        E5   F5         F2    E1   F1    F7    ED  FD   F9   EF   FF   E3   F3	N V . . . . Z C
STA	Pm	AL -> B			A -> W		           85   95         92    81   91    97    8D  9D   99   8F   9F   83   93	. . . . . . . .
STX	Px	XL -> B			X -> W		           86         96			  8E					. . . . . . . .

STY	Px	YL -> B			Y -> W		           84   94				  8C					. . . . . . . .
STZ	Pm	0  -> B			0 -> W		           64   74				  9C  9E				. . . . . . . .
TRB	Pm	/AL /\ B -> B		/A /\ W -> W	           14					  1C					. . . . . . Z .
TSB	Pm	AL V B -> B		A V W -> W	           04					  0C					. . . . . . Z .



  V	logical OR		  B    byte per effective address
  /\	logical AND		  W    word per effective address
  V-	logical exclusive OR      r    relative offset
  +	arithmetic addition	  A    Accumulator, AL low half of Accumulator
  -	arithmetic subtraction    X    Index Register, XL low half of X register
  !=	not equal		  Y    Index Register, YL low half of Y register
  .	status bit not affected   Pc   carry bit
  /	negation		  M/X  effective mode bit in Status Register (Pm or Px)
				  Ws   word per stack pointer
				  Bs   byte per stack pointer

Notes:

  BIT instruction does not affect N and V flags when using immediate
  addressing mode. When using other addressing modes, the N and V flags
  are respectively set to bits 7 and 6 or 15 and 14 of the addressed memory
  depending on mode (byte or word).

  For all Read/Modify/Write instruction addressing modes except accumulator
    Add 2 cycles for E=1 or E=0 and Pm=1 (8-bit mode)
    Add 3 cycles for E=0 and Pm=0 (16-bit mode).

  Add one cycle when indexing across page boundary and E=1 except for STA and
  STZ instructions.

  If E=1 then 1 -> SH and XL -> SL If E=0 then X -> S regardless of Pm or Px.

  Exchanges the carry (Pc) and E bits. Whenever the E bit is set the following
  registers and status bits are locked into the indicated state:
  XH=0, YH=0, SH=1, Pm=1, Px=1.

  Add 1 cycle if branch is taken. In Emulation (E= 1 ) mode only --add 1 cycle
  if the branch is taken and crosses a page boundary.

  Add 1 cycle in Emulation mode (E=1) for (dir),y; abs,x; and abs,y addressing
  modes.

  With TSB and TRB instruction, the Z flag is set or cleared by the result
  of AAB or AAW.
  For all Read/Modify/Write instruction addressing modes except accumulator --
    Add 2 cycles for E=1 or E=0 and Pm=1 (8-bit mode)
    Add 3 cycles for E=0 and Pm=0 (16-bit mode).



	 Table 6. Branch, Transter, Push, Pull, and Implied Addressing Mode Instructions

				   Operation		    Operation					    Status
Mnemonic Bytes M/X   Cycles  8 Bit		Cycles   16 Bit	    Implied Stack Relative	N V M X D I Z C Mnemonic

BCC (6)	  2	-	2    PC+r -> PC		2	PC+r -> PC		    90		. . . . . . . .	BCC
BCS (6)	  2	-	2    PC+r -> PC		2	PC+r -> PC		    B0		. . . . . . . .	BCS
BEQ (6)	  2	-	2    PC+r -> PC		2	PC+r -> PC		    F0		. . . . . . . .	BEQ
BMI (6)	  2	-	2    PC+r -> PC		2	PC+r -> PC		    30		. . . . . . . .	BMI

BNE (6)	  2	-	2    PC+r -> PC		2	PC+r -> PC		    D0		. . . . . . . .	BNE
BPL (6)	  2	-	2    PC+r -> PC		2	PC+r -> PC		    10		. . . . . . . .	BPL
BRA (6)	  2	-	2    PC+r -> PC		2	PC+r -> PC		    80		. . . . . . . .	BRA
BVC (6)	  2	-	2    PC+r -> PC		2	PC+r -> PC		    50		. . . . . . . .	BVC
BVS (6)	  2	-	2    PC+r -> PC		2	PC+r -> PC		    70		. . . . . . . .	BVS

CLC	  1	-	2    0 -> Pc		2	0 -> Pc		18			. . . . . . . 0	CLC
CLD	  1	-	2    0 -> Pd		2	0 -> Pd		D8			. . . . 0 . . .	CLD
CLI	  1	-	2    0 -> Pi		2	0 -> Pi		58			. . . . . 0 . .	CLI
CLV	  1	-	2    0 -> Pv		2	O -> Pv		B8			. 0 . . . . . .	CLV

DEX	  1	Px	2    XL - 1 -> XL	2	X - 1 -> X	CA			N . . .	. . Z . DEX
DEY	  1	Px	2    YL - 1 -> YL	2	Y - 1 ->Y	88			N . . .	. . Z . DEY
INX	  1	Px	2    XL + 1 -> XL	2	X + 1 -> X	E8			N . . . . . Z .	INX
INY	  1	Px	2    YL + 1 -> YL	2	Y + 1 -> Y	C8			N . . .	. . Z . INY

NOP	  1	-	2    no operation	2	no operation	EA			. . . . . . . .	NOP
PEA	  3	-	5    W->Ws, S-2 ->S	5	same		    F4			. . . . . . . .	PEA
PEI	  2	-	6    W->Ws, S-2 ->S	6	same		    D4			. . . . . . . .	PEI

PER	  3	-	6    W ->Ws, S-2 ->S	6	same		    62			. . . . . . . .	PER
PHA	  1	Pm	3    AL->Bs, S-1 ->S	4	A ->Ws, S-2 ->S	    48			. . . . . . . .	PHA
PHB	  1	-	3    DB->Bs, S-1 ->S	3	same		    8B			. . . . . . . .	PHB
PHD	  1	-	4    D ->Ws, S-2 ->S	4	same		    OB			. . . . . . . .	PHD

PHK	  1	-	3    PB->Bs, S-1 ->S		same		    4B			. . . . . . . . PHK
PHP	  1	-	3    P ->Bs, S-1 ->S	3 	same		    08			. . . . . . . .	PHP
PHX	  1	Px	3    XL->Bs, S-1 ->S	4	X-Ws, S-2 -> S	    DA			. . . . . . . . PHX
PHY	  1	Px	3    YL->Bs, S-1 ->S	4	Y ->Ws, S-2 ->S	    5A			. . . . . . . .	PHY

PLA	  1	Pm	4    S+1 ->S, Bs -> AL	5	S+2 ->S, Ws->A	    68			N . . . . . Z .	PLA
PLB	  1	-	4    S+1 ->S, Bs -> DB	4 	same		    AB			N . . . . . Z .	PLB
PLD	  1	-	5    S+2 ->S, Ws -> D	5 	same		    2B			N . . . . . Z .	PLD
PLP	  1	-	4    S+1 ->S, Bs -> P	4 	same		    28			N V M X D I Z C	PLP

PLX	  1	Px	4    S+1 ->S, Bs -> XL	5	S+2 ->S, Ws->X	    FA			N . . . . . Z .	PLX
PLY	  1	Px	4    S+1 ->S, Bs -> YL	5	S+2 ->S, Ws->Y	    7A			N . . . . . Z .	PLY

SEC	  1	-	2    1 -> Pc		2	1 -> Pc		38			. . . . . . . 1	SEC
SED	  1	-	2    1 -> Pd		2	1 -> Pd		F8			. . . . 1 . . .	SED
SEI	  1	-	2    1 -> Pi		2	1 -> Pi		78			. . . . . 1 . .	SEI

TAX	  1	Px	2    AL -> XL		2	A -> X		AA			N . . . . . Z .	TAX
TAY	  1	Px	2    AL -> YL		2	A -> Y		A8			N . . . . . Z .	TAY
TCD	  1	-	2    A -> D		2	A -> D		5B			N . . . . . Z .	TCD

TCS	  1	-	2    A -> S			A -> S		1B			. . . . . . . .	TCS
TDC	  1	-	2    D -> A		2	D -> A		7B			N . . . . . Z .	TDC
TSC	  1	-	2    S -> A		2	S -> A		3B			N . . . . . Z .	TSC
TSX	  1	Px	2    SL -> XL		2	S -> X		BA			N . . . . . Z .	TSX

TXA	  1	Pm	2    XL -> AL		2	X -> A		8A			N . . . . . Z .	TXA
TXS	  1	-	2    see note 4		2	X -> S		9A			. . . . . . . .	TXS
TXY	  1	Px	2    XL -> YL		2	X -> Y		9B			N . . . . . Z .	TXY
TYA	  1	Pm	2    YL -> AL		2	Y -> A		98			N . . . . . Z .	TYA

TYX	  1	Px	2    YL -> XL		2	Y -> X		BB			N . . . . . Z .	TYX
XCE	  1	-	2    see note 5		2	see note 5	FB			. . . . . . . C	XCE

See Notes on page 13.




		Table 7. Other Addressing Mode Instructions


							    Status
Mnemonic  Addressing Mode	Opcode Cycles Bytes	N V M X D I Z C	   Mnemonic	Function

 BRK	stack			  00	7/8	2	. . . . 0 1 . .		BRK	See discussion in Interrupt Processing Sequence section.
 BRL	relative long		  82	 3	3	. . . . . . . .		BRL	PC+r -> PC where -32768 < r < 32767.
 COP	stack			  02	7/8	2	. . . . 0 1 . .		COP	See discussion in Interrupt Processing Sequence section.
 JML	absolute indirect	  DC	 6	3				 	JMLW -> PC, B-PB

 JMP	absolute		  4C	 3	3	. . . . . . . .		JMP	W -> PC
 JMP	absolute indirect	  6C	 5	3	. . . . . . . .		JMP	W -> PC
 JMP	absolute indexed indirect 7C	 6	3	. . . . . . . .		JMP	W -> PC
 JMP	absolute long		  5C	 4	4				JMP	W -> PC, B -> PB

 JSL	absolute long		  22	 8	4	. . . . . . . .		JSL	PB -> Bs, S-1 -S, PC -> Ws, S-2 -> S, W -> PC,	B -> PB
 JSR	absolute		  20	 6	3	. . . . . . .		JSR	PC -> Ws, S-2 -> S, W -> PC
 JSR	absolute indexed indirect FC	 6	3	. . . . . . . .		JSR	PC -> Ws, S-2 -> S, W -> PC
 MVN	block			  54  7/byte	3	. . . . . . . .		MVN	See discussion in Addressing Mode section
 MVP	block			  44  7/byte	3	. . . . . . . .		MVP
 REP	immediate		  C2	 3	2	N V M X D I Z C		REP	P /\ /B -> P
 RTI	stack			  40	6/7	1	N V M X D I Z C		RTI	S+1 -> S, Bs -> P, S+2 -> S, Ws -> PC,
											 if E=0 then S+1 -> S, Bs -> PB

 RTL	stack			  6B	 6	1	. . . . . . . .		RTL	S+2 -> S, Ws~1 -> PC, S+1 -> S, Bs -> PB

 RTS	stack			  60	 6	1	. . . . . . . .		RTS	S+2 -> S, Ws+1 -> PC
 SEP	immediate		  E2	 3	2	N V M X D I Z C		SEP	PVB -> P
 STP	implied			  DB	 3+	1	. . . . . . . .		STP	Stop the clock. Requires reset to continue.
 WAI	implied			  CB	 3+	1	. . . . . . . .		WAI	Wait for inte-rupt. RDY held low until Interrupt.
 XBA	implied			  EB	 3	1	N . . . . . Z .		XBA	Swap AH and AL. Status bits reflect final condition of AL.

Notes on page 13.



				16
